This invention relates to power supply filtering for serial interfaces in a programmable logic device (PLD), and more particularly to power supply filtering for PLDs having several different types of serial interface.
PLDs frequently incorporate serial interfaces to accommodate different serial input/output (“I/O”) standards. In addition to lower-speed serial I/O standards, such as the LVDS (Low-Voltage Differential Signalling) standards, including, e.g., SPI-4.2 (System Packet Interface 4.2) and HyperTransport 1.0, there are several different high-speed serial I/O standards with speeds ranging from 1 Gbps up to as much as 10 Gbps. At one time, the trend was toward “universal” serial interfaces that could handle the entire range of I/O standards and speeds that might be encountered. However, the current trend, exemplified, e.g., by above-incorporated application Ser. No. 11/402,417, is to provide a plurality of different interfaces for different serial I/O standards, with the number of each type of interface differing according to the expected amount of use of the different standards. Thus, generally, the lower the speed called for by a particular I/O standard, the more interfaces for that standard would be provided.
Various noise sources exist that may affect the I/O interfaces. First, there may be noise sources on the PLD die itself. Second, there may be noise sources introduced in the device packaging. Third, in an end-user system in which the PLD is mounted on a circuit board, there may be noise sources introduced by other circuitry on that circuit board. Moreover, which interface is affected by a particular noise source is a function of the frequency of the noise source and its relationship to the frequency (i.e., the speed or data rate) of the interface.
One way of dealing with the effect of noise on an I/O interface is to filter the I/O interface power supply. However, previous attempts at power supply filtering have been global in nature—i.e., they have been “one-size-fits-all” approaches that apply a single power supply filtering scheme to the PLD or to the system containing the PLD.